Field
Embodiments of the present disclosure generally relate to a method and apparatus for forming low resistivity crystalline silicon films for display devices.
Description of the Related Art
Advanced and next generation displays require both active and passive devices capable of operating at high currents and/or high speeds for switching, direction or response, which put high demands for low resistivity silicon thin films, in addition to high mobility low temperature poly-Si (LTPSi) and metal oxide channel materials.
Doped amorphous silicon (a-Si), due to its high deposition rates and good large-area uniformity, has been widely used for the ohmic contact layer in doped a-Si thin film transistor (TFT) devices, for the n+/p+ junction layers and for the silicon/transparent conductive oxide (Si/TCO) ohmic contact layers in PIN or NIP photodiode sensors. However, the resistivity of n+ or p+ doped a-Si films could not be lowered enough because of low doping efficiency, to meet the requirements for high current or high speed display devices, such as LTPSi TFT, OLED, piezoresistive touch sensors, photodiode sensors. Crystalline silicon, such as microcrystalline or nanocrystalline silicon (mc-Si or nc-Si), is known to have much higher doping efficiency due to the crystalline phase, and hence much lower resistivity (or higher conductivity) that is at least 1-4 orders of magnitude lower than for a-Si counterparts. Highly conductive mc-Si layers are usually deposited at very low rates (<60-120 A/min) from highly hydrogen-diluted plasma using various plasma enhanced chemical vapor deposition (PECVD) methods. Furthermore, it is challenging to grow mc-Si or nc-Si layers at high rates and uniformly regarding crystallinity and thickness over large-area substrates.
Therefore, there is a need in the art for an improved apparatus and method for forming low resistivity crystalline silicon films for display devices.